1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having an under stepped gate for preventing a “not open fail” of a landing plug contact by preventing a gate from leaning and a method of manufacturing the same.
2. Description of the Prior Art
Recently, as semiconductor memories, such as DRAMs, have been highly integrated, a conventional flat type transistor may cause lack of a threshold voltage in a cell area and reduction of refresh time. For this reason, various studies have been performed to ensure the threshold voltage and refresh characteristics adaptable for highly integrated semiconductor devices.
For instance, a STAR (step-gated asymmetry recess) cell structure has recently been proposed. As shown in FIG. 1, the STAR cell structure is achieved by recessing a part of an active area of a substrate 1 defined by an isolation layer 2. That is, the STAR cell structure is achieved by recessing both longitudinal edge portions of the active area such that the active area has a stepped structure and forming a gate 6 on the stepped portion of the active area to increase an effective channel length of a MOSFET device.
The STAR cell structure can reduce a short channel effect so that it can obtain a desired threshold voltage at a relatively low threshold voltage dose. In addition, the STAR cell structure can reduce an electric field applied to a MOSFET device, thereby lengthening the refresh time above three times as compared with that of the conventional flat type cell structure.
In particular, the STAR cell structure can be obtained by adding a simple process to conventional processes or changing the conventional processes, so that the STAR cell structure is easily applicable. For this reason, the STAR cell structure has recently been spotlighted as an effective solution for ensuring the threshold voltage and refresh characteristics adaptable for highly integrated semiconductor memory devices.
However, when fabricating the above STAR cell structure, as shown in FIG. 1, the gate 6 is formed on the stepped portion of the active area, causing the leaning of the gate 6.
If the gate 6 formed on the stepped portion of the active area leans, a contact part may not be exposed in the following landing plug contact (LPC) process, which is called an “LPC not open fail”.
In FIG. 1, reference numerals 1 to 5 represent a semiconductor substrate, an isolation layer, a gate insulation layer, a gate conductive layer and a hard mask layer, respectively.